Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs), programmable input/output blocks (IOBs), and like type programmable elements. The CLBs and IOBs are interconnected by a programmable interconnect structure. An FPGA may also include various dedicated logic circuits, such as memories, digital clock managers (DCMs), and input/output (I/O) transceivers. Notably, an FPGA may include one or more embedded processors. The programmable logic of an FPGA (e.g., CLBs, IOBs, and interconnect structure) is typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells. The bitstream is typically stored in an external nonvolatile memory, such as an erasable programmable read only memory (EPROM). The states of the configuration memory cells define how the CLBs, IOBs, interconnect structure, and other programmable logic are configured.
Some circuit designs targeted for implementation in an FPGA may include one or more chains of flip-flops. A chain of flip-flops may be used in a circuit design to implement the functionality of a shift register. When the circuit design is translated for implementation in an FPGA, a flip-flop may occupy a particular area within the FPGA. For example, a flip-flop in a circuit design may occupy a particular percentage of a CLB in an FPGA. As the number of flip-flops in a chain increases, and as the number of flip-flop chains in a circuit design increases, the area in the FPGA occupied by these chains increases.
Some FPGAs may be capable of implementing dedicated shift register logic. For example, some FPGAs may include the capability of implementing one or more shift registers in a CLB (e.g., using look up tables (LUTs)). The shift register capability may be referred to as a shift register primitive of the FPGA. A shift register primitive may occupy less implementation area in an FPGA than a corresponding chain of flip-flops. For example, if a flip-flop occupies x % of a CLB, then a chain of four flip-flops occupies 4×% of a CLB. In contrast, a shift register primitive configured to store at least four values (i.e., functionally equivalent to the chain of four flip-flops) may occupy only x % of a CLB. As such, it is desirable to use shift register primitives in place of flip-flop chains when implementing a design for an FPGA in order to reduce the area used by the design. Resources in an FPGA, such as CLB resources, may be scarce, making it advantageous to reduce design implementation area as much as possible.
Accordingly, there exists a need in the art for a method and apparatus that maps flip-flop logic onto shift register logic when translating a circuit design for implementation in a PLD, such as an FPGA.